The power consumption of integrated circuits (ICs) is an important design consideration in most electronic products. For example, the power consumption of memory devices used in portable electronic products such as portable computers, personal digital assistants (PDAs) and wireless phone affects the amount of time these products can be used before the batteries must be recharged. Even in products that are not battery operated, the power consumption of memory devices should me minimized to reducing heating effects and conserve energy.
The power consumption of a memory device generally increases as its memory capacity and operation speed increase. In a dynamic random access memory (DRAM), for example, memory cells are refreshed by activating rows of memory cells in rapid sequence. Refresh operations consume a relatively large amount of power: a pair of bit lines are switched to complementary voltages and then equalized each time the memory cells of a row are refreshed. As the number of cells in a memory array increases, so too does the amount of power required to refresh the cells. Moreover, the power consumption also increases as the cell activation rate increases. Accordingly, as the operational speed and memory capacity of DRAMs continue to increase, an ever increasing amount of power is required to refresh memory cells.
Referring to FIG. 1A, a memory cell MC of a typical DRAM includes one switch transistor T and a capacitor C. The switch transistor T is connected to a row or a word line WL. Charges stored on the capacitor C are transmitted to a column or a bit line BL through the switch transistor T when word line WL is activated. When WL is deactivated, charges are ideally prevented from being transmitted to the bit line. However, the charges stored on a capacitor leaked through well-known leakage paths, and this prevents the memory cell from retaining its data indefinitely. Thus, a DRAM is known as a volatile memory.
The amount of time that the memory cells in a DRAM can retain data before they must be refreshed can be determined before the device is installed in a product. There is, however, a certain amount of variation in the refresh time for the different cells within a device. FIG. 1B which shows the statistical distribution of data retention times for memory cells in an exemplary DRAM. From FIG. 1B, it is apparent that the data retention or refresh times of the memory cells are within a wide range. Memory cells having the shortest data retention time are referred to as “weak” cells and are indicated by the region marked with a dotted line in FIG. 1B.
To provide reliable storage of data, conventional volatile memories use the refresh times of the weakest memory cells as the time basis for refreshing all of the cells in the memory array. Thus, the majority of cells having relatively long data retention times are refreshed more frequently than is necessary, thereby unnecessarily increasing the amount of power required for refresh operations.